The present invention is directed to memory devices and, more particularly, to dynamic random access memory (DRAM) structures formed in a substrate.
Dynamic random access memory devices (DRAMs) typically include a semiconductor memory cell array formed of a plurality of memory cells arranged in rows and columns and include a plurality of bit lines as well as a plurality of word lines that intersect the bit lines. Each memory cell of the array is located at the intersection of a respective word line and a respective bit line and includes a capacitor for storing data and a transistor for switching, such as a planar or vertical MOS transistor. The word line is connected to the gate of the switching transistor, and the bit line is connected to the source or drain of the switching transistor. When the transistor of the memory cell is switched on by a signal on the word line, a data signal is transferred from the capacitor of the memory cell to the bit line connected to the memory cell or from the bit line connected to the memory cell to the capacitor of the memory cell.
When data stored in one of the memory cells is read onto one of the bit lines, for example, a potential difference is generated between the bit line of the respective memory cell and the bit line of another memory cell which form a bit line pair. A bit line sense amplifier connected to the bit line pair senses and amplifies the potential difference and transfers the data from the selected memory cells to a data line pair.
An advantage of DRAMs over other types of memory technology is their low cost because of the simplicity and scaling characteristics of the memory cell. Though the DRAM memory cell is based on simple concepts, the actual design and implementation of such cells typically requires a highly complex DRAM design and process technology.
An example of current DRAM technology is a buried capacitor DRAM memory in which memory bits are constructed in pairs to allow sharing of a bit line contact. The sharing of the bit line contact significantly reduces the overall cell size. Typically, the memory bit pair includes an active area (AA), a pair of active word lines and a pair of passing/field word lines, a bit line contact, a metal or polysilicon bit line, and a pair of cell capacitors.
The bit line pitch, i.e., the width of the bit line plus the distance between adjacent bit lines, typically determines the active area pitch and the capacitor pitch. The active area width is typically adjusted to maximize the transistor drive and minimize the transistor-to-transistor leakage.
The word line pitch typically determines the space available for the bit line contact, the transistor length, the active area space, and the capacitor length. Each of these dimensions must be optimized to maximize device capacitance, minimize device leakage and maximize process yield.
As semiconductor devices become increasingly smaller, the distance between adjacent bit lines decreases, thereby increasing the capacitance between adjacent bit lines, known as the bit line-to-bit line capacitance. The increased capacitance induces delays which are more critical for such smaller devices because the devices operate at higher speeds so that the time between the read and/or sense signals on the bit line decreases. It is therefore desirable to reduce the bit line-to-bit line capacitance.
The use of low dielectric-constant insulator materials, known as low-k materials, as the insulator between the bit lines in place of TEOS or other insulators has been proposed. However, such low-k materials are typically unable to withstand temperatures above 400° C. and thus cannot withstand the subsequent annealing steps that are carried out at much higher temperatures. Therefore, such low-k materials are presently unsuitable to serve as insulators between the bit lines.
It is therefore desirable to provide a DRAM structure and fabrication process that avoids these problems.